The present invention relates to a semiconductor memory device, and more particularly, to a core voltage generation circuit for generating core voltage.
A semiconductor memory device is used in storing data in a variety of applications. Such a semiconductor memory device is widely used in desktop computers, notebook computers and portable electronic apparatuses. Therefore, there is a need for the semiconductor memory device of large capacity, high speed, small size and low power.
In order to achieve the semiconductor memory device of low power, a method for minimizing power consumption in a core area of the memory device has been proposed. The core area includes a memory cell, a bit line and a word line, and is designed according to an ultra-fine design rule. To design an ultra-fine semiconductor memory device for performing high frequency operations, it is essential to lower power source voltage.
The semiconductor memory device uses an internal voltage of a voltage level adequate for operations in an internal circuit of the semiconductor memory device, which is generated by an external power supply voltage (VDD) lower than a certain voltage level. Specifically, a memory device, such as a dynamic random access memory (DRAM), which utilizes a bit line sense amplifier, uses a core voltage (VCORE) to sense cell data. When a word line is enabled, data in a plurality of memory cells connected to the word line are transferred to bit lines, and then the bit line sense amplifiers sense and amplify voltage differences of bit line pairs. Generally, thousands of bit line sense amplifiers are operated at the same time. Thus, a large amount of current is consumed at a time at a core voltage terminal to drive pull-up power lines of the bit line sense amplifiers.
FIG. 1 is a circuit diagram of a conventional core voltage generation circuit.
Referring to FIG. 1, the conventional core voltage generation circuit includes a comparator 10, an amplifier 11 and a feedback voltage generator 12. The comparator 10 differentially compares a feedback voltage of half core voltage (½ voltage level of a potential at a core voltage terminal) and a reference voltage (VREFC) (of ½ voltage level of a target core voltage; 0.75 V). The amplifier 11 generates an amplified core voltage of approximately 1.5 V in response to an output signal of the comparator 10. The feedback voltage generator 12 divides the amplified core voltage, and outputs the feedback voltage having ½ voltage level of the potential at the core voltage terminal to monitor the core voltage. The conventional core voltage generation circuit further includes a control switch 13 configured to control operations of the comparator 10.
The core voltage generation circuit determines operation point of the comparator 10 using an external power supply voltage VDD applied to an NMOS transistor MN1 constituting the control switch 13.
As the NMOS transistor MN1 is turned on in response to the external power supply voltage VDD and the NMOS transistor MN2 is turned on in response to the reference voltage VREFC applied from the outside, drain voltages of the transistors MN1 and MN2 are lowered. That is, the potential of the node N1 is lowered. Then, a low level signal is applied to a gate of a PMOS transistor MP3 to turn on the PMOS transistor MP3, thereby increasing the core voltage VCORE output from the core voltage generation circuit.
As the core voltage VCORE is increased, the feedback voltage is also increased to thereby turn on an NMOS transistor MN3. As the NMOS transistor MN3 is turned on, a potential of the node N2 is decreased to decrease a voltage level applied to gates of the PMOS transistors MP1 and MP2. As a result of the decrease of the voltage level at the gates of the PMOS transistors MP1 and MP2, the PMOS transistors MP1 and MP2 are turned on, thereby increasing a potential of the node N1 gradually. That is, a gate voltage of the PMOS transistor MP3 is gradually increased. Such operations are repeated until the feedback voltage becomes equal to the reference voltage VREFC.
The conventional core voltage generation circuit determines an operation point of the comparator 10 using the external power supply voltage VDD applied to the gate of the NMOS transistor MN1 constituting the control switch 13. However, the external power supply voltage VDD inevitably has an error range within a certain range because it is applied from the outside.
Therefore, the turn on characteristic (current path) of the NMOS transistor MN1 is determined by the external power supply voltage VDD applied to the control switch 13. The turn on characteristic of the NMOS transistor MN1 affects the turn on characteristic of the NMOS transistor MN2 in the comparator 10, and thus the turn on characteristic of the PMOS transistor MP3 in the amplifier 11.
However, as described above, the conventional core voltage generation circuit determines the operation point of the comparator 10 only through the NMOS transistor MN1 regardless of the voltage level of the external power supply voltage VDD. Therefore, the conventional core voltage generation circuit has the limitation that the core voltage VCORE may become instable according to the external power supply voltage VDD.
Such a conventional core voltage generation circuit performs the same controls regardless of whether the external power supply voltage is higher or lower than the reference voltage. That is, the generation of the core voltage is controlled by the two-stage amplifier using the same internal bias driver. Therefore, the conventional core voltage generation circuit has the limitation that the output level of the core voltage is not constant, for example, the output core voltage is high when the external power supply voltage is high, and the output core voltage is low when the external power supply voltage is low. Particularly, the amplifier generating the core voltage includes only one PMOS transistor. Accordingly, if the amplification characteristic of the PMOS transistor is set with reference to a high level region of the external power supply voltage, insufficient drivability may be caused in a low level region of the external power supply voltage. In addition, if the amplification characteristic of the PMOS transistor is set with reference to the low level region of the external power supply voltage, noise and power consumption may be increased.